PARIS – Esterel Technologies SA, French supplier of development tools for safety-critical software, plans to unveil its ESL (Electronic System level) to implementation design flow, now supporting the IP-XACT specification from the SPIRIT Consortium, at this week’s Design Automation Conference in San Francisco (California).

Esterel Studio is a design environment based on the Esterel language. It is optimized for hardware IPs (such as DMAs, protocols, cache controllers, I/O subsystems, etc.) dedicated at capturing formal design specifications, enabling formal verification of properties very early in the design phase, and automating the production of synthesizable RTL (VHDL and Verilog), both for prototyping and production purposes.

In April 2006, Esterel Technologies joined the SPIRIT Consortium as a reviewing member to access the IP-XACT specification and upgrade its Esterel Studio solution in a view to support the new specifications for improved multi-vendor IP design and tool flow integration. Now that Esterel Studio fully supports the IP-XACT specification from The SPIRIT Consortium, SoC architects and designers can quickly import Esterel Studio designed IP into their architectural design, exploration and SoC integration tools, explained Esterel.

At DAC, Esterel Technologies plans to demonstrate the full benefits of the ESL synthesis with the integration of an Esterel IP into ARM RealView SoC Designer and Synopsys coreAssembler.

“Esterel Studio provides an automated ESL to RTL flow starting from a formally verified IP executable specification”, declared Günther SIEGEL, Esterel Studio’s CTO, in a statement. “In the demonstration we will show at The SPIRIT Consortium general meeting at DAC, we generate SystemC models and VHDL/Verilog designs with IP-XACT descriptions, from a single Esterel Studio model. We checked smooth interoperability between three EDA partner tools supporting the IP-XACT standard, which proves the effectiveness of The SPIRIT Consortium Specifications.”