HONOLULU — Pressured by a need to boost I/O bandwidth and keep chip die sizes in check, some Ethernet controller vendors are turning to embedded DRAM as an on-chip buffer memory. If the trend catches on, the networking chips could prove an important application for semiconductor companies thwarted from widely deploying their embedded-DRAM technology because of its high cost.

Level One Communications (Sacramento, Calif.), a subsidiary of Intel Corp., claims it will become the first company to offer a Gigabit Ethernet chip with embedded DRAM as a way to quickly move transient packet data between ports. However, Mosaid Technologies Inc. (Kanata, Ontario) is also in the final stages of developing a Gigabit Ethernet controller with embedded DRAM for an undisclosed customer. The semiconductor company has taken the lead on the design with Toshiba Corp. acting as a foundry. Both Level One and Mosaid talked about their plans at the recent Symposium on VLSI Technology here.

Level One hopes to unveil the details of its chip in August at Stanford University's Hot Chips Symposium. The eight-port controller, which will be manufactured on Taiwan Semiconductor Manufacturing Co.'s 0.25-micron process, will run at 125 MHz and include 32 Mbits of embedded DRAM.

Level One is also designing a follow-up device based on 0.18-micron technology, said Dinesh Venkatachalam, the company's senior manager of internetworking operations. Level One is using an embedded-DRAM design from Silicon Access, which will present at Hot Chips its own network address processor using embedded DRAM for fast-forwarding table lookups.

Some industry observers peg the cost of a chip with embedded DRAM as 50 percent higher than pure logic.

Nevertheless, Venkatachalam said embedded DRAM has become a requirement for Gigabit Ethernet chips, the fastest-growing segment of the LAN market, because of its density compared with SRAM and its buffering ability for transient data such as ATM packets, which must pass through in 64-byte chunks.

"We offer the highest buffering for every port," he said. "We wanted to get full speed for all ports, all [packet] sizes under all conditions."

The Mosaid chip, meanwhile, should be ready for tapeout next month. It will be the second networking chip the company has designed using embedded DRAM, the first being a switching device for Newbridge Networks, said Richard Foss, chairman of Mosaid.

Foss said he believes networking chips are an emerging application for embedded DRAM because they use transient data and can take advantage of the technology's wide on-chip buses. And unlike graphics chips, where embedded DRAM found its first high-volume use, the market is not so volatile. "I think the networking space is the one, and it will have more stability than graphics," Foss said.

"I don't think that in networking we have any solution besides embedded DRAM at this time," said Level One's Venkatachalam.

Level One expects to have an advantage over competing devices with embedded SRAM from companies like Broadcom and Switchcore, because it was able to add 12 times more memory for the same die area. A typical SRAM cell is made up of six transistors, while a normal DRAM cell consists of one transistor and a stacked capacitor.

Unforeseen hazards

To get that higher density, Level One took the risky path of using a more costly manufacturing process fraught with unforeseen hazards. Chip designers had to come up with new routing paths during layout to overcome signal blockage due to the size of the memory, which takes up one-third of the die area. During fabrication, early wafer yields were below 50 percent because of the mixed memory-and-logic process, a problem that the company partially solved by deactivating bad memory bits in some final chips. The company also learned late in the development cycle that it couldn't get by without using a memory tester.

Despite those problems, Venkatachalam said it was worth the extra time and cost to bring in embedded DRAM. "For our industry we would go with even three times the cost if we could make it," he said.

That's good news for chip vendors that have been pushing embedded-DRAM processes for the last several years with only limited market success. Embedded DRAM got its start in high volume with graphics chips for portable PCs, though in recent years the trend has gone back to using discrete DRAM for the graphics frame buffer.

Robert Bicevskis, director of hardware engineering for graphics-chip maker ATI Technologies Inc., said the cost of embedded DRAM is hard to justify in a price-sensitive PC market. And some graphics vendors found out too late that they did not include enough on-chip memory to buffer 3-D data when that became a requirement, even as their logic performance suffered.

"If you fix yourself on embedded DRAM you've locked yourself in and you will get screwed by your competitors," Bicevskis said. "Accelerex, NeoMagic, Silicon Magic — where are they today?"

For its portable-PC graphics chips, ATI uses a multidie ball-grid array package that houses a discrete graphics IC and 8 Mbytes of known-good-die DRAMs. The traces that connect them, while not as good as on-chip DRAM, consume less power than pc-board traces, the company claims. Using that packaging ATI loses only 1 percent of its chips during assembly and has the flexibility to alter the DRAM configuration, Bicevskis said.

Level One considered using a similar multidie package for its forthcoming Gigabit Ethernet device, but then learned that its volumes were not high enough to generate much interest from assembly companies. The company also considered high-speed Rambus DRAM, which Intel is pushing for main memory in PCs, but was told that the parts would be on allocation, Venkatachalam said.

Vibrant research

While there's still considerable debate over whether embedded DRAM will become a standard process technology, research in the area is vibrant. At the Honolulu conference, Lucent Technologies described a simplified 0.16-micron embedded-DRAM process that has a topology identical to a logic process. A team from Mitsubishi and Matsushita presented their work on a process with a 0.29-micron² DRAM cell, enough density to put 64 Mbits of DRAM and 10 million gates of logic on a chip. Infineon Technologies described a 0.17-micron process with a DRAM cell size of only 0.23 micron². And IBM Microelectronics told how it fabricated high-density DRAM on the bulk area of patterned silicon-on-insulator wafers with fast SOI logic using 0.25-micron design rules.

While many chip vendors are still wary of the cost of embedded DRAM, there could come a time when high-performance logic chips like microprocessors won't be able to do without it. Shekhar Borkar, Intel Fellow and director of the company's circuit research lab, said Intel will likely integrate embedded DRAM in its CPUs after the 0.1-micron technology node.

That's because DRAM cells are denser than SRAM and 10 to 100 times less power hungry than logic circuits. Tomorrow's processors may be 80 percent memory, so making it as dense as possible will be key. "Caches require less power than logic and it's a cheaper way to get performance than logic," Borkar said. "In the same space I can put 10 times more DRAM, so I now start wondering if I should start using embedded DRAM."