Brion Technologies, a provider of optical proximity correction (OPC) tools for manufacturing groups, is coming to the June Design Automation Conference (DAC) with its first product aimed at IC design teams. Called Tachyon Lithography Aware Design (LAD), it aims to help designers discover and correct lithography-induced hot spots before tapeout.

Brion was recently acquired by lithography giant ASML and is now a wholly owned subsidiary of that company. Brion's flagship product is Tachyon, a hardware-assisted OPC verification and application tool. Tachyon LAD uses the same hardware accelerator, but does not require the use of Tachyon on the manufacturing side.

Tachyon LAD analyzes GDSII data, and models how the lithography process will reproduce a design on silicon. It displays silicon contours and lithography hot spots, and shows designers and EDA tools how to fix layouts in order to resolve problems.

While Brion has traditionally focused on the post-tapeout world, moving into design is a "natural next step," said Mike Gianfagna, Brion vice president of design business. "If we can package up our knowledge and core competency in a way that the IC designer can use that information to understand what the manufacturing process will do to a design, you have the opportunity to create a design that's more compatible with the manufacturing process," he said.

The result, said Gianfagna, will be designs that are inherently more printable with higher fidelity across larger lithography process windows. This adds up to better yields and the ability to extract better performance from processes, he said.

Brion is offering Tachyon LAD through its initial EDA partners: Cadence Design Systems, Magma Design Automation, and Japanese provider Tool Corp. "Brion is entering the design market as a supplier of core modeling technology, but not as a supplier of IC implementation tools," Gianfagna said. "We plan to leverage existing tools and channels, and partner with EDA companies to introduce this information into their design flows."

Tachyon LAD provides several types of information. One is silicon contours, which provide representations of what a drawn image in GDSII will actually look like as a printed image in silicon. Another is lithography hot spots, showing areas most likely to cause catastrophic defects. A third is descriptions of how to move edges in order to fix the hot spots.

The tool does not actually repair IC layouts, Gianfagna noted. "We provide hints, which are scripts that describe the error, the severity of the error, and suggestions of different ways to move edges to correct errors," he said. "We leave it to the EDA tool to move the edges." Depending on the EDA partner, he said, the repair could take place during the routing phase or during post-processing.

While the core technology for the OPC and the lithography simulation come from Brion, the calibration data that tells the tool how to work comes from the foundry partner, Gianfagna said. Outside of the IDM environment, Brion can protect this data through encryption, he noted.

While other design for manufacturability (DFM) providers offer lithography aware tools, Brion offers a couple of advantages, Gianfagna said. One is EDA vendor independence. Another is the availability of accurate, calibrated models. "We have a large footprint in many major semiconductor companies and foundries, and we build our models from the ground up," he said. "We can make them very early in the process."

Tachyon LAD will be available for beta testing in July, with cost varying according to configuration.

ASML announced its plans to acquire Brion in December, and completed the acquisition earlier this year.