LONDON — ARM plc will start sampling its lead partners AMBA Adaptive Verification IP for on-chip communication during the third quarter.

ARM (Cambridge, England) suggested at this week's Design Automation Conference in San Diego the system-level verification framework is the industry's only engine for extracting and applying traffic profile information to predict how systems will perform.

The first EDA vendor to ensure the IP functions smoothly within its verification methodology will be Mentor Graphics. The IP will be available generally from the fourth quarter.

ARM said the IP complements existing random or directed-random methods with a powerful approach to reducing verification time, improving verification confidence, and enabling the explosion in SoC size and complexity to continue.

"Tomorrow’s complex consumer devices must run multiple applications simultaneously, which requires fast and efficient on-chip communication," said Jonathan Morris, general manager of the System Design Division at ARM. "To minimize risk, designers need a complete toolbox, including on-chip communication and verification IP, plus a tools framework that enables them to configure, analyze and verify their complex SoC devices."

ARM will license Adaptive Verification IP as an add-on to the RealView SoC Designer tool. The company said the IP will also be made available under licence for use within all popular verification tool flows from the leading EDA vendors.

The IP is written C++ and encapsulated in System Verilog for RTL compatibility.

Separately at DAC, ARM and Taiwanese foundry UMC (Hsinchu) said a test chip built with ARM's Silicon on Insulator libraries was taped-out successfully on UMC's 65-nanometer SOI process.

The test chip consists of a set of ARM physical IP that uses a standard cell library, an I/O library and a single-port SRAM memory compiler. The companies say the tape-out at UMC represents the next step towards mainstream adoption of nanometer SOI technology for improved speed and power in complex SOCs.

UMC has been developing SOI technology for many years. This collaboration began in January 2006, when UMC started a strategic partnership with Soisic. ARM continued this partnership after acquiring Soisic and partnering with Soitec in October 2006, and has begun to offer SOI libraries alongside its full range of physical IP for bulk CMOS processes.

The ARM standard cells used in the test chip support multi-VT and multi-power supply circuit designs, the I/O is 3.3V signal tolerant and the memory compiler is optimized for high-speed and low-power consumption.

The companies say initial circuit analysis indicates that the design saves up to 20 percent in area and 30 percent in power consumption, compared to a part produced to reach the same performance on bulk CMOS at 65nm. SOI technology also offers up to 28 percent speed boost with 10 percent power reduction over bulk CMOS.