Hybrid Chips for 5G Mobile

In most current devices, silicon-based CMOS chips are used for computing, but they prove to be inefficient for lighting and communications, resulting in performance loss and thermal problems. This is why the current 5G mobile devices on the market become very hot during use and turn off after a short time.

The electronic devices of the near future will have to contain sensors that transmit data wirelessly to a control center. This means that they will have to combine RF capabilities with a small form factor and low operating power. A clean and promising approach to achieve all these objectives is to create single chips that combine the capabilities of silicon CMOS with those of III-V devices. These III-V chips consist of elements in the 3rd and 5th columns of the periodic table such as gallium nitride (GaN) and indium gallium arsenide (InGaAs). Thanks to their unique properties, they are exceptionally suitable for optoelectronics (LEDs) and communications (5G), thus increasing the overall efficiency of the system.

Chips and 5G networks

5G is not simply a faster 4G. Networks running 5G will be up to 20 times faster than the existing 4G network, enabling video download speeds up to 10 times faster. 5G is considered a “new” web, the infrastructure candidate for managing the Internet of things (IoT).

The 5G network will lead to sophisticated cloud app services, an intelligent and connected society with smart cities, self-driving cars, and new industrial platforms. There’s an imperative to build the ICs necessary to enable all of that, but there is still a lot of design work to do and test & measurement to perform. Among the most challenging obstacles are the ongoing evolution of the standards, the adoption of millimeter-wave (mmWave) technology, and controlling costs.

The Singapore-MIT Alliance for Research and Technology (Smart), MIT’s Research Enterprise in Singapore, has announced the successful development of a commercially viable way to manufacture silicon circuitry integrated with high-performance III-V devices.

“Most current devices use silicon-based CMOS chips that are used for computing, but they are not efficient for illumination and communications. This results in low efficiency and heat generation,” said Fayyaz Singaporewala, senior innovation manager of the Low Energy Electronic Systems (LEES) Interdisciplinary Research Group at Smart.

The power density of GaN technology has made it a turning point for the industry, and the number of such devices used in phased array applications and other domains is increasing. Finally, the price is reaching a level that makes the technology attractive even to the budget-conscious consumer market. These technologies have the potential to combine high-speed converters with microwave components in a single die, including power amplifiers and biasing circuits.

“Silicon CMOS technology can achieve power-added efficiency (PAE) of ~20% while GaN devices can achieve PAE of 50% or more. But silicon CMOS technology has the advantage of higher integration of added functionalities (such as on-chip digital control, adaptive matching, digital pre-distortion, etc). Smart’s technology allows us to leverage the best of both these worlds which is critical for 5G technology,” said Kenneth Lee, senior scientific director of the LEES group at Smart.

5G must provide not only the highest data rates but also a latency of less than 1ms. Due to the properties of Internet protocols, lower latency is essential to achieve higher data transfer rates. In a car, where it’s important to exploit communication for safety, in particular, to drastically reduce the chances of fatal accidents.

“The new devices will enable 5G devices to be a working reality as current technology cannot keep up with the requirements of 5G. Our technology will allow chips that can meet all applicable specifications of 5G within the tight power and space budgets of complex mobile devices that are coming up. Silicon III-V chips will enable the creation of the mobile 5G devices that will power cars, mobile devices etc, and would accelerate the adoption of 5G,” Lee said.

The technology is based mainly on two layers of silicon and III-V materials on separate substrates, together in a 1-micron stack. The process can use existing production tools with a decisive reduction in costs and high-performance electronic systems. An overview of the LEES processing scheme is shown in figure 1.

Figure 1: (a) A 1 µm-thick silicon CMOS layer is bonded to a III-V-on-silicon wafer, fabricated using epitaxy. (b) Windows are opened in the CMOS-free areas to expose the underlying III-V layers, and III-V devices are then fabricated. (c) The dielectric layer is deposited. (d) W-plugs are created to contact III-V devices. (e) The dielectric is deposited and flattened using chemical-mechanical polishing. (f) The silicon foundry connects the silicon CMOS and III-V devices together by typical interconnections to complete the integration process.

Smart LEES has a thermal/reliability group dedicated to studying the thermal profile of its chips and devising robust thermal management solutions. The control of the III-V device layout allows the creation of thermally-efficient devices, and CMOS + III-V integration design rules have also been established to mitigate thermal problems. “Our thermal/reliability group,” said Lee, “has also developed front- and back-side thermal spreading/heat extraction technologies to reduce hotspots and allow for cooler device operation.”

The hybrid circuits would also be able to operate with better stability and less noise, with a consequently significant increase in the functionality, complexity, and performance of the circuit, all achieved without having to reduce the size of the device or increase the transistor count.

Currently, Smart’s research focuses on two families of III-V materials: the nitride family, which is aimed at high-power applications and blue and green LEDs; and the arsenide-phosphide family, intended for applications such as very high-frequency power amplifiers, low-noise amplifiers, and yellow and red LEDs.

A challenge was how to approach the CMOS silicon layers and the III-V materials. The success comes from the fabrication of silicon CMOS devices first, to the point just before the back end interconnection, so that an interlayer dielectric covers the silicon CMOS transistors.

Figure 2: SMART has developed a series of CAD tools for implementing these new chips

Subsequently, the wafers are transferred to the Smart structure for integration and III-V processing. The transfer of the silicon CMOS layers on each wafer to the III-V ones involves a series of wafer bonding, oxide deposit, and chemical-mechanical polishing phases. The bond is made with a direct and improved fusion process through subsequent annealing (Figure 2).

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